Design And Implementation Of A Convolutional Encoder With Viterbi Decoder

dc.contributor.author Ahmed, Hamza
dc.date.accessioned 2014-04-30T12:25:36Z
dc.date.available 2014-04-30T12:25:36Z
dc.date.issued 2014-04-30
dc.description in this project Convolution encoding with forward error correction Viterbi decoding was designed using trace back survivor method with 16-bits trellis decoding. The encoder and decoder designs were implemented on a Spartan 3AN FPGA Starter kit (supported with XC3S700AN). Verilog language was used as a design entry. The system was implemented on the kit using direct programming technique. en_US
dc.description.abstract Communication systems plays a major role in our lives specially that we live in the informational revolution era, nowadays communication systems have reached extremely high data rates; however it’s important to ensure that data reach destination correctly, for this purpose channel coding used by adding redundancy bits to ensure that any error occurs during transmission will be detected then corrected. The use of re-transmission methods is not efficient and has large latency measure up to the rising speed and data rates of communication links, the need of new techniques arise here to be compatible with those systems, in this project Convolution encoding with forward error correction Viterbi decoding was designed using trace back survivor method with 16-bits trellis decoding. The encoder and decoder designs were implemented on a Spartan 3AN FPGA Starter kit (supported with XC3S700AN). Verilog language was used as a design entry. The system was implemented on the kit using direct programming technique. en_US
dc.identifier.uri http://hdl.handle.net/123456789/113
dc.subject Design And Implementation Of A Convolutional Encoder With Viterbi Decoder en_US
dc.subject University,Khartoum en_US
dc.title Design And Implementation Of A Convolutional Encoder With Viterbi Decoder en_US
dc.type Thesis en_US
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