Study of Fast packet switches architectures for Asynchronous Transfer mode

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Elbakri, Nassir Mohammed
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Broadband ISDN networks, of which ATM is the accepted transfer mode solution, require fast packet switches to move the ATM cells along their respective virtual paths. The prime purpose of an ATM switch is to route incoming cells (packets more generally) arriving on a particular input link to the output link, which is also called the output port, associated with the appropriate route. The subject of this thesis is to discuss the three basic techniques that have been proposed to carry out the switching (routing) function: space-division, shared-medium, and shared-memory. The basic example for a space-division switch is a crossbar switch, which has also served circuit-switched telephony networks for many years. The inputs and outputs in a crossbar switch are connected at switching points called crosspoints, resulting in a matrix type of structure. New decomposed crossbar switches architecture is developed recently so as to minimize the input and output cell contention, this new architecture is discussed in this thesis. The operation of a shared-medium switch, on the other hand, is based on a common high-speed bus. Cells are launched from input links onto the bus in round-robin fashion, and each output link accepts cells that are destined to it. A more enhanced architecture of this type; a TDM-Based Multibus Packet Switch is discussed in this project. The shared-memory (SM) switch, consists of a single dual-ported memory shared by all input and output lines. Packets arriving on all input lines are multiplexed into a single stream that is fed to the common memory for storage; inside the memory, packets are organized into separate output queues, one for each output line. Simultaneously, an output stream of packets is formed by retrieving packets from the output queues sequentially, one per queue; the output stream is then demultiplexed, and packets are transmitted on the output lines. This project presents a survey of the buffer management methods that have been proposed for shared-memory packet switches. Several buffer management policies are described, and their strengths and weaknesses are examined. The performances of various policies are evaluated using computer simulations. A comparison of the most important schemes is obtained with the help of the simulation results and the results provided in the literature. The survey concludes with a discussion of the possible future research areas related to the Fast packet switch architectures.
packet switches,architectures,Asynchronous,Transfer