OFDM Modem Design and Implementation using Field Programmable Gate Arrays (FPGA)

Abstract

Current and future communication schemes tend to use OFDM systems in order to provide high baud rates, making use of the existing infrastructure, and less inter symbol interference. OFDM provides high bandwidth efficiency because the carriers are orthogonal to each other and multiple carriers share the data among themselves. The main advantages of this transmission technique is resistant to significant ISI because of the presence of the guard interval at the beginning of each OFDM symbol and an OFDM receiver requires only one modulator and demodulator, in contrast with other multicarrier systems. The main objective of this project is to design and implement a base band OFDM transmitter and receiver using FPGA. A Matlab/Simulink simulation of the modem is carried out in order to analyze baseband processing of the proposed modem; simulation results illustrate the Bit Error Rate (BER) for AWGN channel. The core processing blocks of an OFDM system, which are the FFT block, IFFT block, and the synchronization block. The FFT / IFFT decimation-infrequency (DIF) with Radix-22 algorithm is analyzed in detail to produce a solution that is suitable for FPGA implementation, and the symbol detection algorithm based on power level is implemented, as well as the other parts of the modem. The FPGA implementation of the project is performed using Very High Speed Integrated Circuit (VHSIC) Hardware Descriptive Language (VHDL). This performance of the coding is analyzed from the result of timing simulation using Xilinx – ISE Simulator. The different modem components has been successfully implemented in Spartan-3 FPGA and separately tested, and the results were good.